Makefile


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# causes weird file size, smaller than stripped?
ifeq ($(DEBUG),)
  ccflags-y += -g
endif

# Makfile assignments:
#  := value at right is expanded and assigned at declaration time
#   = value at right is expanded only when it is used, hence it is a reference
#  ?= value at right is assigned only if the variable doesn't have a value
#
#

# objects that are part of hello module (hello.o)
hello-y += main.o debug.o

# .ko module to be created
obj-m := hello.o

KERNELDIR ?= /lib/modules/$(shell uname -r)/build

# '-C' changes the dir
# '-M' causes the the kernel's toplevel Makefile to move back into this dir
#      before trying to build 'modules' target
all:
	make -C $(KERNELDIR) KCPPFLAGS="-I$(CURDIR)" M=$(PWD) modules

clean:
	make -C $(KERNELDIR) M=$(PWD) clean